1. Field of the Invention
The present invention relates to logic diagram display methods, programs, and apparatuses in which a text file of a circuit module described in a hardware description language (HDL) is inputted to render a graphical logic diagram on a screen. Particularly, an object of the present invention is to provide a logic diagram display method, program, and apparatus allowing selection of a cell to be arranged on the diagram, rendering of a logic circuit, arrangement and movement of an instance, and appropriate display of attributes of pins and nets.
2. Description of the Related Arts
Conventionally, for a large-sized logic circuit, as a design scheme in place of a circuit diagram, text-based design operations using a hardware description language HDL, such as Verilog-HDL, have been performed. A design operation by the HDL is normally performed according to the following procedure.
(1) Generate an HDL file (function description file) by describing functions of a circuit module on a text editor in a hardware description language.
(2) Confirm the operation by using an HDL simulator of the HDL file.
(3) Generate a net list by using a logic synthesis tool from the HDL file with its operation having been confirmed. In such a design operation using a hardware description language, the following operations are repeated: with the use of a logic diagram display apparatus that reads an HDL file with the function of the circuit module described on a text base and graphically renders a logic circuit on a screen as a design support apparatus, in an in-progress stage in the design operation or a design completion stage, the function-described module is input on the screen to graphically render its logic diagram; on the logic diagram, the contents of the function description is checked; a circuit change or a circuit correction is made as required on the logic diagram; and the checked or corrected logic circuit is then again outputted as an HDL file. Conventional technologies related to the above include, for example, a circuit representation text generation system in Patent Document 1. In this circuit representation text generation system, an interaction is made with an input device while an original text of a circuit representation is displayed on a display screen, thereby setting pin connection information for an unconnected pin described in the original text and generating a circuit representation text. Here, as an instance name (unique name) of a circuit cell to be described in the text, a location (row and column number) on the diagram is used with an association between the cell and the arrangement location.
However, the conventional logic diagram display apparatuses that support a designing operation using a hardware description language have the following problems. First, when an HDL file of a module is inputted to graphically display a logic diagram, if it is desired to newly arrange a certain instance for the logic diagram being rendered, a cell of that instance has to be selected. In the conventional cell selection method, a cell is directly selected from a list of cells stored in a library. If the number of cell types is small, selection is easy. However, the library normally has stored therein as many as several hundreds of cells, thereby posing problems that, since the number of cell types is large, selection is extremely difficult, and erroneous cell selection tends to occur. Also, when an HDL file of a module is inputted to graphically display a logic diagram, data (database), attributes, control data (pragma), and others dedicated to the logic diagram are conventionally required to be inputted apart from the HDL file. The reason for this is that, since a general hardware description language does not have diagram information indicative of arrangement locations on the diagram. When a logic diagram is tried to be rendered with an HDL file as an input, rendering processing is performed under a condition set by an apparatus side, and therefore a logic diagram may not able to be rendered as expected. Moreover, when the HDL file is corrected, rendering processing is performed under a condition set by an apparatus side, thereby posing a problem of making it difficult to render an uncorrected portion always in a same manner. To get around these problems, in the system of Patent Document 1, the location (row and column number) on the diagram is used as the instance name (unique name) of the circuit cell, thereby providing a correspondence between the text and the logic diagram. However, the instance name (unique name) and the location (row and column number) on the diagram can be separately registered. In the case of conversion to a function description file (HDL file) without a location (row and column number), there is a problem that it is not easy to know the original logic diagram from the function description file. Also, in rendering a logic diagram, when an instance is arranged on a diagram, its instance name is specified by a designer or, in the case of no specification, an instance name is automatically provided. Here, the instance means a componentized module in Verilog-HDL, and using a module as a component configuring another module is called instantiation. However, when an HDL file is outputted from the generated logic diagram, the HDL file does not have diagram information, such as diagram arrangement locations, thereby posing a problem that it is not easy to know the original logic diagram from the HDL file. Furthermore, in the case where, after a logic diagram is generated and outputted as an HDL file, a layout design is performed by using a logic synthesis tool to evaluate a slack value of a pin or a wiring length of a net, it is conventionally required to evaluate the slack value and wiring length information on a text base by returning to the HDL file. Therefore, when an HDL file is inputted before layout designing to correct the rendered logic diagram, there is a problem that it is difficult to correct the logic diagram in consideration of the slack value and wiring length information.